SOI wafers have recently been used to produce highly integrated CMOSs, ICs, high breakdown voltage devices and the like. A concrete structure of an SOI wafer is comprised of a three-layer structure in the depth direction of the wafer as follows: a silicon single crystal layer (hereinafter referred to as an SOI layer) that is a surface layer and is used as an active layer providing an area for fabricating a device; a buried insulator layer (hereinafter sometimes referred to as a Box layer in the case of a silicon oxide film) such as an oxide film put under the silicon single crystal layer; and another silicon single crystal layer (hereinafter referred to as a support substrate) is placed under the buried insulator layer. The SOI wafer with such a structure has characteristics such as a low parasitic capacitance and a high radiation resistance. Therefore effects such as high-speed, low power-consumption performance, latch up suppression are expected and the SOI wafer is promising as a substrate for a high-performance semiconductor device.
As a method for producing the SOI wafer, for example, the following bonding methods are known. Namely, two mirror-polished silicon single crystal wafers (a silicon single crystal wafer to serve as an SOI layer (a bond wafer) and a silicon single crystal wafer to serve as a support substrate (a base wafer)) are prepared and an oxide film is formed on a surface of at least one of the silicon single crystal wafers. Next, after the silicon single crystal wafers are bonded via the oxide film, a bonding heat treatment is conducted in order to increase bonding strength. Then, the bond wafer is thinned to obtain an SOI wafer having an SOI layer formed. Examples of methods for thinning are as follows: a method where grinding, polishing, or the like are performed on the bond wafer until a desired thickness is obtained; and a method, which is called an ion implantation delamination method (for example, Japanese Patent No. 3048201), where a delamination layer is formed by ion-implanting hydrogen or helium in advance before bonding, thinning is conducted by a delamination heat treatment at a temperature lower than the temperature of the bonding heat treatment and a delamination of the bond wafer at the delamination layer, and then the above-mentioned bonding heat treatment is conducted.
Although the SOI wafer has a lot of structural advantages in view of electrical characteristics as described above, the SOI wafer has structural disadvantages in view of resistance to contamination with metal impurities. This is because diffusion rates of metal impurities are generally slower in silicon oxide than in silicon. Thereby, in the case of a contamination from an SOI layer surface, the metal impurities accumulate in the thin SOI layer due to the difficulty for the metal impurities to pass the Box layer. Thus a harmful effect of metal contamination is increased as compared with a silicon substrate having no SOI structures. Therefore it is one of the more important qualities in the case of an SOI wafer to have the ability of capturing metal impurities and removing the metal impurities from the area to serve as an active layer for a semiconductor device (gettering ability).
In each gettering method generally used for a silicon substrate having no SOI structures (oxide precipitation, high-density boron addition, a back surface polycrystalline silicon film, and the like), a gettering layer is introduced on the support substrate opposite to the active layer. However, even if a gettering layer is introduced on the support substrate according to the similar techniques, the above-mentioned gettering layer does not function fully due to the difficulty for the metal impurities to pass the Box layer, thus there is a problem in that these techniques are not to be applied to an SOI wafer as they are.
In order to address such a problem, in methods for producing an SOI wafer by a bonding method, there have conventionally been proposed methods where a gettering area is introduced in the neighborhood of the SOI layer.
For example, there is proposed a method where a polycrystalline silicon film is formed on a surface of the bond wafer before bonding using a CVD method (chemical vapor deposition method) and a polycrystalline silicon layer is introduced in an interface area of the SOI layer with the Box layer by bonding the bond wafer and the base wafer via an oxide film using a surface having the polycrystalline silicon film formed thereon as a bonding surface to produce an SOI wafer in which the polycrystalline silicon layer has an extrinsic gettering effect for the SOI layer (see, e.g., Japanese Patent Application Laid-Open Publication No. H6-275525).
However, in a method in which a polycrystalline silicon layer is introduced in the neighborhood of the Box layer by a CVD method mentioned above, due to the inconstancy of a film thickness of the polycrystalline silicon layer produced by a CVD method, a complicated process, as is represented by mirror polishing required before bonding, has been required. Such being the case, there has been a problem in that the cost is increased and productivity is lowered. There has also been a problem in that variation in crystalline interface influences the mirror polishing process to widen variation of a thickness of the polycrystalline silicon layer, leading to variation in a thickness of the SOI layer.